1. Field of the Invention
The present invention relates to Gate Turn-Off (GTO) thyristor switches, and more particularly, to high power, high temperature Silicon Carbide (SiC) GTO thyristor switches.
2. Description of the Related Art
Thyristors are devices used for switching AC or DC power, and are used in high power conditioning circuits, high voltage systems, and traction circuits. Thyristors have a p/n/p/n junction sequence and three terminals (an anode, a cathode, and a gate). Upon application of a current pulse to the gate terminal, a forward current condition is established between the anode and the cathode.
In a standard thyristor, the gate loses control to turn off the device once the current is initially pulsed to the gate to turn on the forward conduction between the anode and cathode. A reverse bias voltage must be placed across the anode-tocathode path in order to turn off the device.
However, in a GTO thyristor, the forward conduction between the anode and the cathode is cut off by merely reversing the gate bias, without having to reduce the main current below a certain threshold level. This feature distinguishes GTO thyristors from other types of switching devices, such as a silicon-controlled rectifier. GTO thyristors normally begin conduction by receiving a trigger input and function as diodes thereafter.
SiC GTO thyristors are an improvement over Silicon GTO thyristors because they switch faster, handle higher power and can function at higher temperature. U.S. Pat. No. 5,539,217 (to Edmond, et al.) and U.S. Pat. No. 5,831,289 (to Agarwal) disclose additional information regarding SiC thyristors, and the contents of these patents are hereby incorporated by reference in their entireties.
The voltage drop between the anode and the cathode in prior art SiC GTO thyristors (such as those disclosed in the above-referenced patents) is about 3V, which is typical for high power thyristor devices. This voltage drop results in a switching power loss, which becomes a dominating factor affecting the device junction temperature at high operating frequencies. As the rated voltage of a thyristor increases, the thickness of a drift region formed adjacent to the anode or cathode (and having opposite conductivity to the anode or cathode) increases dramatically, as does its resistance.
Accordingly, it is an object of the present invention to develop a SiC GTO thyristor which has improved efficiency for use in high power applications.
To this end, according to the present invention, there is provided a Silicon Carbide (SiC) Gate Turn-Off (GTO) thyristor and method for providing such thyristor having at least four doped regions which alternate between a p-type doping and an n-type doping, with the regions being at least partially overlaid. The first, second and third doped regions are epi-layers with the substratum or substrate comprising the fourth region. An anode is arranged on the first region, and a base is arranged on the second region. A controlling gate is arranged on the third region, and a cathode is arranged on the fourth region. A current divider divides the load current between the anode and the base. This current division reduces the voltage drop of a portion of the load current passing through the thyristor, allowing for the switching of higher current densities than in prior art thyristors, faster switching speeds and reduced junction temperatures.
More particularly, the present invention provides a Silicon Carbide (SiC) Gate Turn-Off (GTO) thyristor structure comprising: a substrate formed of SiC having at least three epilayer arranged thereon as first, second and third planar doped regions, respectively, said substrate comprising a fourth doped region, and each of said first, second, third and fourth doped regions having a first side and a second side opposite to the first side, the first, second, third and fourth doped regions being disposed in a sequential arrangement to at least partially overlap one another to form a stack with the first side of the second region adjacent the second side of the first region, the first side of the third region adjacent the second side of the second region, and the first side of the fourth region adjacent the second side of the third region, and the at least first, second, third and fourth doped regions providing current paths, in a direction of the sequential arrangement, alternating between p-type and n-type regions; an anode arranged on the first side of the first region; a base terminal arranged on the first side of the second region, one of the first and second regions being a p-type region and the other of the first and second regions being an n-type region; a gate arranged on the first side of the third region for controlling an on/off state of the thyristor; a cathode arranged on the second side of the fourth region; and current dividing means for dividing a current, flowing from a load, between the anode and the base terminal, the current dividing means being connected at a first end to the anode and the base terminal, and having a second end for being connected, during operation, to the load, so that only a portion of the load current flows to the anode.
This device may be arranged such that the current entering the anode flows through an odd number of p/n or n/p junctions as it travels through the first, second, third and fourth doped regions, and the current entering the base terminal flows through an even number of p/n or n/p junctions as it travels through the first, second, third and fourth doped regions to either the cathode or anode.
In this device, the first region may be a p-type region, the second region an n-type region, the third region a p-type region, and the fourth region an n-type region. The current dividing means may comprise first and second resistors, the first resistor being connected at a first end to the anode, and the second resistor being connected at a first end to the base terminal, and the first and second resistors being adapted to be connected at respective second ends to a same point of the load so as to divide the load current. The first resistor may have a resistance greater than a resistance of the second resistor.
The second region may be more highly doped with n-type material than the third region is doped with p-type material, and the second region may be thicker than the third region.
The dopant concentration of the first region is approximately 1xc3x971019 cmxe2x88x923; the dopant concentration of the second region may range from about 1xc3x971017 cmxe2x88x923 to about 5xc3x971018 cm xe2x88x923; the dopant concentration of the third region may range from about 1xc3x971017 cmxe2x88x923 to about 2xc3x971019 cmxe2x88x923; and the dopant concentration of the fourth region may range from about 1xc3x971018 cm to about 5xc3x971018 cmxe2x88x923. An additional region arranged between said second and fourth regions may be provided, and the additional region has a concentration of less than about 5xc3x971015 cmxe2x88x923 . 
The device may further comprise a gate control means for providing pulses to the gate to turn the thyristor on and off. The gate control means may comprise a voltage source and a gate resistor connected between the voltage source and the gate. The device may further comprise a power source means for generating a load current for input to the anode and the base terminal via the current dividing means.
According to the present invention there is further provided a method of providing an improved Silicon Carbide (SiC) Gate Turn-Off (GTO) thyristor, comprising the steps of:
(a) providing a substrate formed of SiC having at least three epi-layers arranged thereon as first, second, third doped regions, and the substrate comprising a fourth doped region, wherein each of the first, second, third and fourth doped regions having a first side and a second side opposite to the first side, the first, second, third and fourth doped regions being disposed in a sequential arrangement to at least partially overlap one another to form a stack with the first side of the second region adjacent the second side of the first region, the first side of the third region adjacent the second side of the second region, and the first side of the fourth region adjacent the second side of the third region, and the at least first, second, third and fourth doped regions providing current paths, in a direction of the sequential arrangement, alternating between p-type and n-type regions;
(b) arranging an anode on the first side of the first region;
(c) arranging a base terminal on the first side of the second region;
(d) arranging a gate on the first side of the third region for controlling an on/off state of the thyristor;
(e) arranging a cathode on the second side of the fourth region; and
(f) providing a current dividing circuit connected at a first end to the anode and the base terminal, and having a second end adapted for connection to a load, so that a total load current which flows to the. thyristor is divided between the anode and the base terminal.
The method may be such that the current entering the anode may flow through an odd number of p/n or n/p junctions of the first, second, third and fourth doped regions, and the current entering the base terminal may flow through an even number of p/n or n/p junctions as it travels through the first, second, third and fourth doped regions.
Step (a) may further comprise: doping the first region to form a p-type region; doping the second region to form an n-type region; doping the third region to form a p-type region; and doping the fourth region to form an n-type region. The second region may be doped so as to be more highly doped with n-type material than the doping of the third region is doped with p-type material; and the second region may be provided with a thickness which is greater than a thickness of the third region.
The dopant concentration provided to the first doped region may be greater than about 1xc3x971019 cmxe2x88x923. The dopant concentration of the second doped region may range from about 1xc3x971017 cmxe2x88x923 and about 5xc3x971018 cmxe2x88x923 and the concentration of the third doped region may range from about 1xc3x971017 cmxe2x88x923 to about 2xc3x971019 cmxe2x88x923, and the concentration of the fourth doped region may range from about 1xc3x971018cmxe2x88x923 to about 5xc3x971019 cmxe2x88x923.
An additional region may be provided between the second and fourth regions having a concentration of less than about 5xc3x971015 cmxe2x88x923.
Step (f) may further comprise: dividing the current by providing first and second resistors connected at each of their respective first ends at a same point of a load, and connecting the first resistor at its second end to the anode, and connecting the second resistor at its second end to the base terminal. The first resistor may have a resistance which is greater than a resistance of the second resistor.
The method may further comprise providing pulses for controlling the gate to turn on and off the thyristor.
Step (g) may include providing a voltage source and a gate resistor connected between the voltage source and the gate.